edf1as thru EDF1DS vishay semiconductors formerly general semiconductor document number 88578 www.vishay.com 19-apr-02 1 miniature glass passivated ultrafast surface mount bridge rectifiers reverse voltage 50 to 200v forward current 1.0a maximum ratings and thermal characteristics (t a = 25? unless otherwise noted) parameter symbol edf1as edf1bs edf1cs EDF1DS unit maximum repetitive peak reverse voltage v rrm 50 100 150 200 v maximum rms voltage v rms 35 70 106 140 v maximum dc blocking voltage v dc 50 100 150 200 v maximum average forward output rectified current at t a = 40? (note 2) i f(av) 1.0 a peak forward surge current single half sine-wave superimposed on rated load (jedec method) t j = 150? i fsm 50 a rating for fusing (t < 8.3ms) i 2 t10a 2 sec typical thermal resistance per leg (note 1) r ja 38 r jl 12 ?/w operating junction and storage temperature range t j , t stg 55 to +150 ? electrical characteristics (t a = 25? unless otherwise noted) max. instantaneous forward voltage drop per leg at 1.0a (note 2) v f 1.05 v maximum dc reverse current t a = 25? 5.0 a at rated dc blocking voltage t a = 125? i r 1.0 ma max. reverse recovery time at i f = 0.5a, i r = 1.0a, i rr = 0.25a t rr 50 ns notes: (1) p.c.b. mounted with 0.2 x 0.2 (5.0 x 5.0mm) copper pad areas (2) pulse test: 300 s pulse width, 1% duty cycle features ?plastic package has underwriters laboratory flammability classification 94v-0 ?this series is ul listed under recognized component index, file number e54214 ?glass passivated chip junctions ?high surge overload rating-50 amperes peak ?ideal for printed circuit boards ?superfast recovery times for high efficiency ?high temperature soldering guaranteed: 260?/10 seconds at 5 lbs. (2.3kg) tension mechanical data case: molded plastic body over passivated junctions terminals: plated leads solderable per mil-std-750, method 2026 polarity: polarity symbols marked on body mounting position: any weight: 0.014 oz., 0.4 g packaging codes/options: 27/1.5k per 13" reel (16mm tape) 45/50 ea. per tube-bulk 0.255 (6.5) 0.245 (6.2) 0.013 (0.330) 0.009 (0.241) 0.060 (1.524) 0.040 (1.016) 0.404 (10.3) 0.013 (0.330) 0.003 (0.076) 0.047 (1.20) 0.040 (1.02) 0.205 (5.2) 0.195 (5.0) 0.335 (8.51) 0.320 (8.13) 0.130 (3.3) 0.120 (3.05) 45 o 0.386 (9.80) dimensions in inches and (millimeters) case style dfs 0.404 max. (10.26 max.) 0.205 (5.2) 0.195 (5.0) 0.047 min. (1.20 min.) 0.060 min. (1.52 min.) mounting pad layout
edf1as thru EDF1DS vishay semiconductors formerly general semiconductor www.vishay.com document number 88578 2 19-apr-02 ratings and characteristic curves (t a = 25 c unless otherwise noted) 20 40 60 80 100 120 140 160 0 0.5 1.0 1 10 100 0 10 20 30 40 50 60 0.4 0.6 0.8 1.0 1.2 1.4 0.01 0.1 1 10 0 20 40 60 80 100 0.1 1 10 100 1,000 1 0.1 10 100 200 10 5.0 0 15 20 25 30 fig. 5 - typical junction capacitance per leg junction capacitance (pf) reverse voltage (v) t j = 25 c f = 1.0 mhz vsig = 50mvp-p 1.0 cycle i pk / i av = resistive or inductive load 0.51 x 0.51" (13 x 13mm) copper pads fig. 3 - typical forward characteristics per leg instantaneous forward current (a) instantaneous forward voltage (v) t j = 25 c pulse width = 300 s 1% duty cycle fig. 1 - derating curves output rectified current average forward output current (a) ambient temperature ( c) fig. 2 - maximum non-repetitive peak forward surge current peak forward surge current (a) number of cycles at 60 hz t j = 150 c single sine-wave (jedec method) fig. 4 - typical reverse leakage characteristics per leg instantaneous reverse leakage current ( a) percent of rated peak reverse voltage (%) t j = 125 c t j = 25 c 0.75 0.25 capacitive loads i pk / i av = 5.0 i pk / i av = 10 i pk / i av = 20
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